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The structure of RX_STATUS is described in Table 6-3 .
Table 6-3. Structure of RX_STATUS.
Bit
Read/Write
Reset value
Bit
7
RX_CRC_VALID
R
0
3
6
R
0
2
5
TRAC_STATUS
R
0
1
4
R
0
0
RX_STATUS
reserved
RX_STATUS
Read/Write
Reset value
R
0
R
0
R
0
R
0
Note:
1.
More information to RX_CRC_VALID, see Section 8.2.5 , and to TRAC_STATUS,
see Section 7.2.6 .
On Frame Buffer write access the second byte transferred on MOSI contains the frame
length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8 .
Figure 6-8. Packet Structure - Frame Write Access.
byte 1 (command byte)
byte 2 (data byte)
byte 3 (data byte)
byte n -1 (data byte)
byte n (data byte)
MOSI
MISO
0 1 1 reserved[4:0]
PHY_STATUS
PHR[7:0]
XX
PSDU[7:0]
XX
PSDU[7:0]
XX
PSDU[7:0]
XX
The number of bytes n for one frame access is calculated as follows:
Read Access : n = 5 + frame_length
[PHY_STATUS, PHR byte, PSDU data, LQI, ED, and RX_STATUS]
Write Access : n = 2 + frame_length
[command byte, PHR byte, and PSDU data]
Each read or write of a data byte automatically increments the address counter of the
Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read
access may be terminated (/SEL = H) at any time without affecting the Frame Buffer
content. Another Frame Buffer read operation starts again at the PHR field.
The content of the Atmel AT86RF232 Frame Buffer is overwritten by a new received
frame or a Frame Buffer write access.
Figure 6-9 and Figure 6-10 illustrate an example SPI sequence of a Frame Buffer
access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU.
Figure 6-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU.
/SEL
SCLK
MOSI
MISO
COMMAND
PHY_STATUS
XX
PHR
XX
PSDU 1
XX
PSDU 2
XX
LQI
XX
ED
XX
RX_STATUS
18
AT86RF232
8321A – MCU Wireless – 10/11
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